;================================================================================
; Robert Johnstone
; Simon Fraser University
;
; Copyright 2000 Robert W. Johnstone
;--------------------------------------------------------------------------------

; 2002/07/23
; - modified code so that when include_C is true, the substrate capacitance
; is printed along with the regular capacitance
; 2002/06/04
; - modified code to calculate capacitance when etch holes are not present
; 2002/06/03
; - modified because dbCreateMumpsPin function interface was changed
; 2000/07/01
; - created

unless( boundp( 'admLibraryName )
	warn( "Setting the destination library to default value of ADM" )
	admLibraryName = "ADM"
)

pcDefinePCell(
	list( ddGetObj(admLibraryName) "capacitor" "layout"
	) ; end of list for first argument

	(
		( width			100.0 )
		( height		100.0 )
		( pin_size		20.0 )
		( include_C		t )
		( include_EtchHoles	t )
	) ; end of parameter list

	prog( 
		( pcTechFile pcNet pcShape rodObj
			p0a1_minSpacing p1p0_enclosure p1_nomSpacing p1_nomWidth p1_maxWidth
			p1a1_enclosure p1p2_enclosure p2p0_enclosure p2v_enclosure p2m_enclosure
			v_nomWidth h1_nomWidth
			line tmp w h x y count_x count_y )

		; load tech file rules
		pcTechFile = techGetTechFile( pcCellView )
		p0a1_minSpacing = techGetSpacingRule( pcTechFile "minSpacing" "POLY0" "ANCHOR1" )
		unless(  p0a1_minSpacing  warn("minSpacing rule for POLY0 and ANCHOR1 not set") )
		p1p0_enclosure = techGetOrderedSpacingRule( pcTechFile "minEnclosure" "POLY1" "POLY0" )
		unless(  p1p0_enclosure  warn("minEnclosure rule for POLY1->POLY0 not set") )
		p1_nomSpacing = techGetSpacingRule( pcTechFile "nomSpacing" "POLY1" )
		unless(  p1_nomSpacing  warn("nomSpacing rule for POLY1 not set") )
		p1_nomWidth = techGetSpacingRule( pcTechFile "nomWidth" "POLY1" )
		unless(  p1_nomWidth  warn("nomWidth rule for POLY1 not set") )
		p1_maxWidth = techGetSpacingRule( pcTechFile "maxWidth" "POLY1" )
		unless(  p1_maxWidth  warn("maxWidth rule for POLY1 not set") )
		p1a1_enclosure = techGetOrderedSpacingRule( pcTechFile "minEnclosure" "POLY1" "ANCHOR1" )
		unless(  p1a1_enclosure  warn("minEnclosure rule for POLY1->ANCHOR1 not set") )
		p1p2_enclosure = techGetOrderedSpacingRule( pcTechFile "minEnclosure" "POLY1" "POLY2" )
		unless(  p1p2_enclosure  warn("minEnclosure rule for POLY1->POLY2 not set") )
		p2p0_enclosure = techGetOrderedSpacingRule( pcTechFile "minEnclosure" "POLY2" "POLY0" )
		unless(  p2p0_enclosure  warn("minEnclosure rule for POLY2->POLY0 not set") )
		p2v_enclosure = techGetOrderedSpacingRule( pcTechFile "minEnclosure" "POLY2" "P1P2VIA" )
		unless(  p2v_enclosure  warn("minEnclosure rule for POLY2->P1P2VIA not set") )
		p2m_enclosure = techGetOrderedSpacingRule( pcTechFile "minEnclosure" "POLY2" "METAL" )
		unless(  p2m_enclosure  warn("minEnclosure rule for POLY2->METAL not set") )
		v_nomWidth = techGetSpacingRule( pcTechFile "nomWidth" "P1P2VIA" )
		unless(  v_nomWidth  warn("nomWidth rule for P1P2VIA not set") )
		h1_nomWidth = techGetSpacingRule( pcTechFile "nomWidth" "HOLE1" )
		unless(  h1_nomWidth  warn("nomWidth rule for HOLE1 not set") )

		; check parameters
		p1_nomWidth = if( (p1_nomWidth<0) 0 p1_nomWidth )
		width = if( (width<p1_nomWidth) p1_nomWidth width )
		height = if( (height<p1_nomWidth) p1_nomWidth height )

		; pre-calculations
		line = v_nomWidth + 2 * p2v_enclosure + 2 * p1p2_enclosure

		; create bulk of capacitor
		pcNet = dbCreateNet( pcCellView "C1" )
		dbCreateMumpsPath( pcCellView pcNet
			list(-width*0.5:height*0.5+line*0.5 width*0.5+line*0.5:height*0.5+line*0.5 width*0.5+line*0.5:-height*0.5-line*0.5 -width*0.5:-height*0.5-line*0.5 )
			line )			
		;dbCreatePath( pcCellView "ANCHOR1" list( -width*0.5+p1a1_enclosure:height*0.5+line*0.5 width*0.5+line*0.5:height*0.5+line*0.5 width*0.5+line*0.5:-height*0.5-line*0.5 -width*0.5+p1a1_enclosure:-height*0.5-line*0.5 ) v_nomWidth + 2*(p2v_enclosure+p1p2_enclosure-p1a1_enclosure) )
		;pcShape = dbCreatePath( pcCellView "POLY2" list( -width*0.5+p1p2_enclosure:height*0.5+line*0.5 width*0.5+line*0.5:height*0.5+line*0.5 width*0.5+line*0.5:-height*0.5-line*0.5 -width*0.5+p1p2_enclosure:-height*0.5-line*0.5 ) v_nomWidth + 2*p2v_enclosure )
		;dbCreatePin( pcNet pcShape )
		;pcShape = dbCreatePath( pcCellView "METAL" list( -width*0.5+p1p2_enclosure+p2m_enclosure:height*0.5+line*0.5 width*0.5+line*0.5:height*0.5+line*0.5 width*0.5+line*0.5:-height*0.5-line*0.5 -width*0.5+p1p2_enclosure+p2m_enclosure:-height*0.5-line*0.5 ) v_nomWidth + 2*(p2v_enclosure-p2m_enclosure) )
		;dbCreatePin( pcNet pcShape )
		;dbCreatePath( pcCellView "P1P2VIA" list( -width*0.5+p1p2_enclosure+p2v_enclosure:height*0.5+line*0.5 width*0.5+line*0.5:height*0.5+line*0.5 width*0.5+line*0.5:-height*0.5-line*0.5 -width*0.5+p1p2_enclosure+p2v_enclosure:-height*0.5-line*0.5 ) v_nomWidth )
		dbCreateRect( pcCellView "POLY1" list( -width*0.5:-height*0.5-line width*0.5+line:height*0.5+line ) )

		tmp = pin_size*0.5 - p1p2_enclosure - p2p0_enclosure
		w = width*0.5 + p1a1_enclosure - p0a1_minSpacing
		h = height*0.5 + p1a1_enclosure - p0a1_minSpacing
		dbCreatePolygon( pcCellView "POLY0" list( -width*0.5-pin_size*0.5-p1_nomSpacing:tmp -width*0.5+p1p0_enclosure:tmp -width*0.5+p1p0_enclosure:h w:h w:-h -width*0.5+p1p0_enclosure:-h -width*0.5+p1p0_enclosure:-tmp -width*0.5-pin_size*0.5-p1_nomSpacing:-tmp ) )

		; create other pin
		pcNet = dbCreateNet( pcCellView "C2" )
		dbCreateMumpsPin( pcCellView pcNet -width*0.5-pin_size*0.5-p1_nomSpacing:0 pin_size 0 )

		; put in interior etch holes if required and requested
		if( (include_EtchHoles==t) then
		w = h1_nomWidth * 0.5
		h = h1_nomWidth * 0.5
		count_x = floor( ( width + p1a1_enclosure ) / p1_maxWidth )
		count_y = floor( ( height + 2*p1a1_enclosure ) / p1_maxWidth )
		for( lp_x 1 count_x 
			x = -width*0.5 + lp_x * (width+p1a1_enclosure)/(count_x+1)
			for( lp_y 1 count_y
				y = -height*0.5 - p1a1_enclosure + lp_y * (height+2*p1a1_enclosure) / (count_y+1)
				dbCreateRect( pcCellView "HOLE1" list( x-w:y-h x+w:y+h ) )
			)
		)
		)

		; put capacitance estimate?
		if( (include_C==t) then
			; get relative permittivity
			tmp = if( (include_EtchHoles==t) 1.0 3.7 )
			; get capacitance
			tmp = height * width * tmp * 8.854187818e-12 / 2.0 * 1e-6
			dbCreateLabel( pcCellView '("TMP" "drawing") 0:pin_size sprintf(nil "C = %1.3g" tmp) "centerCenter" "R0" "stick" pin_size*0.5 )
			; calculate the substrate capacitance
			tmp = height * width * 7.5 * 8.8554187818e-12 / 0.6 * 1e-6
			dbCreateLabel( pcCellView '("TMP" "drawing") 0:-pin_size sprintf(nil "Cs = %1.3g" tmp) "centerCenter" "R0" "stick" pin_size*0.5 )
		)

		; add stretch handles
		rodObj = rodGetObj( "" pcCellView )
		rodAssignHandleToParameter(
			?parameter	"width"
			?rodObj		rodObj
			?handleName	list( "centerLeft" "centerRight" )
			?displayName	"width"
			?stretchDir	"x"
			?userFunction	lambda( (SPCInfo) SPCInfo->paramVal + 2*SPCInfo->increment )
		)
		rodAssignHandleToParameter(
			?parameter	"height"
			?rodObj		rodObj
			?handleName	list( "lowerCenter" "upperCenter" )
			?displayName	"height"
			?stretchDir	"y"
			?userFunction	lambda( (SPCInfo) SPCInfo->paramVal + 2*SPCInfo->increment )
		)

		; Create the instNamePrefix property
		dbReplaceProp( pcCellView "instNamePrefix" "string" "capacitor" )
		; set version string
		dbReplaceProp( pcCellView "version" "string" "1.2.1" )
		; body SKILL code returns value t
		return(t)

	) ; end of body-of-SKILL-code prog

) ; ; end of pcDefinePCell