Vancouver, BC, Canada
I do computer architecture and programming languages. I like to develop frameworks and that break down abstraction barriers and rethinks the hardware–software interface. I worked with the Architecture Research Group at Simon Fraser University advised by Arrvindh Shriraman.
During my Phd I worked on High-Level Synthesis (HLS) tools and developed a framework – µIR – that can generate parallel hardware accelerators from your high-level program in C/C++ and Cilk for FPGAs.
|muIR||muIR is a tool to generator hardware accelerator from software programs. muIR-Generator uses muIR as an intermediate representation (IR) to design hardware accelerators. Currently, muIR-Generator supports C/C++ and Cilk programs.|
muIR-lib is a library of hardware components wirtten in Chisel for auto generating highly configurable parallel dataflow accelerator. muIR-lib provides the implementation of the following hardware units:
|muIR-Sim||muIR-sim is a new simulation environment that improves software and hardware integration and simulation accuracy compare to functional simulation. One of the goals of this framework is integration the hardware development process into the software stack from the beginning, allowing features to be incrementally implemented and evaluated as workloads evolve over time.|
|TAPAS||TAPAS is an HLS tool that generates parallel accelerators from parallel programs written in Cilk/Cilk++ language.|
|Chainsaw||A cycle accurate simulator that models the host core, the Chainsaw accelerator, and spatial fabrics of parameterizable size.|