library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity ROM_16x6 is 

port(
		Addr	: in	std_logic_vector(3 downto 0);
		Data	: out	std_logic_vector(5 downto 0)
	);
end ROM_16x6;

architecture arch1 of ROM_16x6 is
	type memory is array (0 to 15) of std_logic_vector(5 downto 0);
	signal ROM: memory;
begin
		ROM(0)  <= "000000";   -- ldi  x0;	-- Since the Data is only taking from ROM(0) to ROM(3), the first 4 ROM have to be ldi, addi and bz instructions.
	    ROM(1)  <= "010001";   -- addi x1;
	    ROM(2)  <= "000000";   -- ldi  x0;
	    ROM(3)  <= "100000";   -- bz   x0;
	    ROM(4)  <= "010001";   -- addi x1; 
	    ROM(5)  <= "010001";   -- addi x1; 
	    ROM(6)  <= "010001";   -- addi x1; 
	    ROM(7)  <= "010001";   -- addi x1; 
	    ROM(8)  <= "011000";   -- addi x8;
	    ROM(9)  <= "000000";   -- ldi  x0;
	    ROM(10) <= "100000";   -- bz   x0;
	    ROM(11) <= "111111";
		ROM(12) <= "111111";
	    ROM(13) <= "111111";
	    ROM(14) <= "111111";
	    ROM(15) <= "111111"; 
	    Data 	<= ROM(to_integer(Addr));
end arch1;