EQM design goals
Dual mode: used in both the 8 x 100 Mbps port controller IC and the 1 x 1 Gbps port controller IC.
Small silicon area: (70K gates + 1024 bits memory).
Reuse memory and circuits between modes as much as possible.
Low latency: no more than 64 clock cycles between QA received to QF granted in an idle system.
Multiple strategies for servicing queues:
- Strict Priority Scheduling
- Weighted Fair Scheduling
- Weighted Priority Scheduling
Reusability: Easy to reuse all or part of the design in another IC.