S U N D A Y , M A Y 2 3 - R E G I S T R A T I O N
Morning Registration (7:00 AM - 12:00 Noon)

Afternoon Registration (12:00 Noon - 5:00 PM)

S U N D A Y , M A Y 2 3 - T U T O R I A L S
Morning Tutorials - Sunday	Room	#Attendees	# Missing speakers
08:30 - 11:30
Tutorial: TUT-1: Design of Continuous-Time Filters from 0.1 Hz to 2.0 GHz	Junior Ballroom C	23
Tutorial: TUT-4: Low Power Video Platforms for Mobile Applications	Port McNeil	25
All Day Tutorials - Sunday
08:30 - 4:15
Tutorial: TUT-9: Microsystems and Nanotechnology Through Applications	Port Alberni	15
Tutorial: TUT-10: Ultrawideband Radio Communications	Junior Ballroom D	54
Afternoon Tutorials - Sunday
1:15 - 4:15
Tutorial: TUT-5: Design for Testability of Analog and Mixed-Signal Integrated Circuits	Junior Ballroom C	12
Tutorial: TUT-6: Clocking and Synchronization issues in sub-100nm System on Chip (SoC) Designs	Junior Ballroom A	15
Tutorial: TUT-7: Cryptography: Circuits and Systems Approach	Junior Ballroom B	6
Tutorial: TUT-8: CMOS Imagers: From Phototransduction to Image Processing	Port McNeil	18
Forum - Sunday
4:30 - 6:00
Forum: FORUM-1: New Era of Technology	Junior Ballroom	111
M O N D A Y , M A Y 2 4 - Registration, Poster Session, and Internet Café
Registration	Registration 7:00-12:00	Registration 12:00 - 5:00
(7:00 AM - 5:00 PM)

Poster Session (9:00 - 5:30) (Pavilion Room - Level 3 - North Tower)
Internet Café (8:00 - 5:30)
M O N D A Y , M A Y 2 4 - S E S S I O N S - Morning
08:00 - 09:00	Room	# Attendees	# Missing speakers
Plenary: Genomic Signal Processing	Grand Ballroom	[1]
09:30 - 11:00
ASP-L1: Pipelined ADC	Grand Ballroom A	85	0
ASP-L2: Analog Filtering Techniques I	Grand Ballroom B	45 (39)	1 [2]
ASP-L3: Voltage References	Grand Ballroom C	37 (50)	1 [3]
COMM-L1: Communication Architectures	Grand Ballroom D	22 (20)	0
VLSI-L1: Low Power Circuits and Architecture	Junior Ballroom A/B	46 (60)	0
VLSI-L2: Video	Junior Ballroom C	33 (40)	0
DSP-L1: FIR Digital Filters	Junior Ballroom D	36 (25)	0
PSEC-L1: Power Integrated Circuits	Finback	25 (31)	0
CAD-L1: Placement and Routing I	Galiano	25	0
NLCS-L1: Oscillators Design and Implementation	Granville	28 (30)	1 [4]
SEN-L1: Image Sensors I	Orca	28 (36)	0
MMSA-L1: Advanced Multimedia Systems: End-to-End Frameworks	Port Alberni	37	1 [5]
Invited Session: INV-1: Spiking Neural Networks I	Port Hardy	38	0
Invited Session: INV-2: Ultra Wideband Systems	Port McNeill	70	1 [6]
11:15 - 12:45
ASP-L4: Pipelined and Folded ADC	Grand Ballroom A	45	1 [7]
ASP-L5: Analog Filtering Techniques II	Grand Ballroom B	24 (30)	0
ASP-L6: Broadband and UWB circuits	Grand Ballroom C	75 (70)	1 [8]
COMM-L2: CDMA Systems	Grand Ballroom D	24 (20)	0
VLSI-L3: Low Power Arithmetic	Junior Ballroom A/B	32 (60)	0
VLSI-L4: MPEG	Junior Ballroom C	43 (55)	0
DSP-L2: IIR Digital Filters	Junior Ballroom D	25 (19)	0
PSEC-L2: Power Converter Control	Finback	30 (29)	0
CAD-L2: Placement and Routing II	Galiano	24 (23)	0
NLCS-L2: PLLs Design, Implementation and Application	Granville	33 (25)	0
SEN-L2: Vision Sensors	Orca	49	0 [9]
MMSA-L2: Multimedia Watermarking and Data Hiding	Port Alberni	22	0
Invited Session: INV-3: Spiking Neural Networks II	Port Hardy	32	0
Invited Session: INV-4: Multirate Systems for Communications	Port McNeill	40	0
M O N D A Y , M A Y 2 4 - S E S S I O N S - Afternoon
2:15 - 3:45
ASP-L7: Flash ADC	Grand Ballroom A	40	0
ASP-L8: Analog Signal Processing I	Grand Ballroom B	35	0 [10]
ASP-L9: Oscillators	Grand Ballroom C	55 (50)	0
COMM-L3: Ultra Wide Band Systems	Grand Ballroom D	29 (40)	0
VLSI-L5: Low Power Buses and Circuits	Junior Ballroom A/B	42 (50)	0
VLSI-L6: Image Processing	Junior Ballroom C	25 (30)	0
DSP-L3: Digital Filters	Junior Ballroom D	30 (50)	0
PSEC-L3: Power Amplifiers	Finback	33 (30)	0
CAD-L3: Analog Modeling, Synthesis & Optimization I	Galiano	18	0
NLCS-L3: Chaos-based Methodologies for Security	Granville	27 (31)	0
SEN-L3: Mems and Sensory Systems	Orca	30 (65)	1 [11]
MMSA-L3: Multimedia Database and Retrival Systems	Port Alberni	22	1 [12]
ASP-L10: Circuit Theory in Electronics	Port Hardy	23 (18)	0
Invited Session: INV-5: Digital Signal Processing for Smart Multi-Media Systems	Port McNeill	20	0
4:00 - 5:30
ASP-L11: CMOS ADC	Grand Ballroom A	55	0
ASP-L12: Analog Signal Processing II	Grand Ballroom B	20 (15)	1 [13]
ASP-L13: Mixed Signal Testing	Grand Ballroom C	18 (20)	0
COMM-L4: Oscillator Design	Grand Ballroom D	65 (63)	0
VLSI-L7: Low Power Codes and Cryptography	Junior Ballroom A/B	25 (27)	1 [14]
VLSI-L8: Coding	Junior Ballroom C	25 (27)	0
DSP-L4: Digital Filter Banks	Junior Ballroom D	32 (25)	0
PSEC-L4: Multilevel Power Converters	Finback	25 (30)	0
CAD-L4: Analog Modeling, Synthesis & Optimization II	Galiano	16 (25)	1 [15]
ASP-L14: General Circuit Theory	Granville	13 (25)	0 [16]
SEN-L4: Chemical, Acoustic, Olfactory and Neuromorphic Sensors	Orca	41 (44)	0
MMSA-L4: Multimedia Communication and Transmission	Port Alberni	48	1 [17]
Invited Session: INV-6: Silicon Implementations of CNN and Programmable Mixed-Signal Vision I	Port Hardy	28 (30)	0
Invited Session: INV-7: Nonlinear Dynamics and Complexity in Network Traffic Modeling and Control	Port McNeill	37	0
5:45 - 7:15 - FORUM
Forum: FORUM-2: The Future of Circuits and Systems	Junior Ballroom	136
T U E S D A Y , M A Y 2 5 - Registration, Poster Session, and Internet Café
Registration (7:00 AM - 5:00 PM)	Registration 7:00-12:00	Registration 12:00 - 5:00

Poster Session (9:00 - 5:30) (Pavilion Room - Level 3 - North Tower)
Internet Café (8:00 - 5:30)
T U E S D A Y , M A Y 2 5 - S E S S I O N S - Morning
08:00 - 09:00
Plenary: CNN Technology for Brain-like Spatial-Temporal Sensory Computing - Present and Future	Grand Ballroom	600
09:30 - 11:00
ASP-L15: Current-Steering DAC	Grand Ballroom A	61 (65)	0
ASP-L16: Bioinspired Circuits	Grand Ballroom B	46 (37)	0
ASP-L17: Voltage and Current Sources I	Grand Ballroom C	73 (70)	0
COMM-L5: Phase Locked Loops (PLL) Circuits and Architectures	Grand Ballroom D	50	0
VLSI-L9: High Performance Low Power	Junior Ballroom A/B	27 (30)	0
VLSI-L10: Arithmetic	Junior Ballroom C	25
DSP-L5: Digital Signal Processing Applications I	Junior Ballroom D	25 (30)	0
PSEC-L5: Systems Theory for Power	Finback	13	0
CAD-L5: Digital Circuits Synthesis & Optimization	Galiano	20 (15)	0 [18]
NLCS-L4: Nonlinear Dynamics and Chaos in Communications I: Modulation and Coding	Granville	28	0
VSPC-L1: Motion Estimation	Orca	40	0
MMSA-L5: Multimedia Coding and Segmentation	Port Alberni	25	0
Invited Session: INV-8: Bionics and Theory of Cellular Neural Networks	Port Hardy	34 (33)	0
Invited Session: INV-9: Current Challenges in Mixed-Signal/RF Design and CAD	Port McNeill	30 (50)	0
11:15 - 12:45
ASP-L18: Digital-to-Analog Converters	Grand Ballroom A	49 (45)	1 [19]
ASP-L19: Design Techniques for ASP	Grand Ballroom B	31 (40)	0
ASP-L20: Voltage and Current Sources II	Grand Ballroom C	42 (40)	0
COMM-L6: Decoding for Communication Systems	Grand Ballroom D	25 (20)	0
VLSI-L11: SoC Design Technology	Junior Ballroom A/B	22 (25)	1
VLSI-L12: Adders and Multipliers	Junior Ballroom C	50	0 [20]
DSP-L6: Digital Signal Processing Applications II	Junior Ballroom D	25 (30)	0
CNN-L1: Bio-inspired and Neuromorphic Array Computers	Finback	50	0 [21]
CAD-L6: Mixed Signal Circuit and Device Modeling	Galiano	39 (40)	0 [22]
NLCS-L5: Nonlinear Dynamics and Chaos in Communications II: Coding and Traffic	Granville	26	0
VSPC-L2: Video over Networks	Orca	30	0
MMSA-L6: Multimedia Understanding and Recognition	Port Alberni	15	0 [23]
Invited Session: INV-10: Frequency-Response Masking Techniques	Port Hardy	26 (27)	0
Invited Session: INV-11: Recent Advances in the Control of Power Electronics	Port McNeill	0	0
T U E S D A Y , M A Y 2 5 - S E S S I O N S - Afternoon
2:15 - 3:45
ASP-L21: Sigma-Delta Converters I	Grand Ballroom A	100	0
ASP-L22: Filter Applications	Grand Ballroom B	24 (25)	0
ASP-L23: Sensor Interface Circuits	Grand Ballroom C	38 (40)	0
COMM-L7: Circuits for Communications	Grand Ballroom D	25 (23)	0
VLSI-L13: Noise in Digital Circuits	Junior Ballroom A/B	20	0
VLSI-L14: Turbo and Viterbi Algorithms	Junior Ballroom C	30	0
DSP-L7: Multidimensional Signal Processing I	Junior Ballroom D	20	0
CNN-L2: Implementation of CNNs and Array Computers	Finback	33 (30)	0
CAD-L7: Interconnect and Clock Distribution	Galiano	23 (25)	0 [24]
NLCS-L6: Nonlinear Circuits Modelling	Granville	26	0
VSPC-L3: Transcoding	Orca	40	0
MMSA-L7: Multimedia Systems and Applications: Advanced Techniques	Port Alberni	20	1 [25]
Invited Session: INV-12: Information Assurance and Data Hiding I	Port Hardy	15 (4)	1 [26]
DSP-L8: Adaptive Signal Processing I	Port McNeill	24	0 [27]
4:00 - 5:30
ASP-L24: Sigma-Delta Converters II	Grand Ballroom A	50	0
ASP-L25: High Gain Amplifiers	Grand Ballroom B	75	0
ASP-L26: Mixed Signal Circuits	Grand Ballroom C	24 (25)	0
COMM-L8: Optical Communication	Grand Ballroom D	12	1 [28]
VLSI-L15: Interconnect	Junior Ballroom A/B	30	0 [29]
VLSI-L16: Cryptography	Junior Ballroom C	20	0 [30]
DSP-L9: Multidimensional Signal Processing II	Junior Ballroom D	16	0
CNN-L3: Complex Spatio-temporal Dynamics in Multi-layer CNNs	Finback	43	0 [31]
CAD-L8: Fundamentals of CAD Algorithms	Galiano	32	0
NLCS-L7: Modelling and Analysis of Nonlinear Systems	Granville	20	0
VSPC-L4: Advanced Video Coding	Orca	40	0
MMSA-L8: VLSI/SOC Implementation for Multimedia Systems I	Port Alberni	30 (28)	0
Invited Session: INV-13: Heterogeneous Systems	Port Hardy	25 (30)	0
DSP-L10: Adaptive Signal Processing II	Port McNeill	0 [32]	0 [33]
T U E S D A Y , M A Y 2 5 - Awards Ceremony / Banquet Dinner
5:30 pm - Volunteers to meet in the Registration area to receive directions for their positioning.
W E D N E S D A Y , M A Y 2 6 - Registration, Poster Session, and Internet Café
	Registration 7:00-12:00	Registration 12:00 - 5:00
Registration (2 Volunteers 7:00 - 5:00)

Poster Session (9:00 - 5:30) (Pavilion Room - Level 3 - North Tower)
Internet Café (8:00 - 5:30)
W E D N E S D A Y , M A Y 2 6 - S E S S I O N S - Morning
08:00 - 09:00
Plenary: Practical Applications of 3-D and 4-D Filters	Grand Ballroom	350
09:30 - 11:00
ASP-L27: ADC Circuits	Grand Ballroom A	43 (45)	0
ASP-L28: High Speed Amplifiers	Grand Ballroom B	27	2 [34]
ASP-L29: RF Frontend Circuits	Grand Ballroom C	38 (26)	0
COMM-L9: Frequency Synthesizers	Grand Ballroom D	24 (35)	1 [35]
VLSI-L17: I/O Circuits	Junior Ballroom A/B	35	0
VLSI-L18: Field Programmable and Reconfigurable	Junior Ballroom C	25	1 [36]
DSP-L11: Digital Signal Processing	Junior Ballroom D	30 (40)	0
CNN-L4: Analysis and Applications of CNNs	Finback	35	0
CAD-L9: Verification, Testing, and Validation	Galiano	7 (8)	2 [37]
NLCS-L8: Nonlinear Circuits Analysis and Design	Granville	31	0
VSPC-L5: Encoder Optimization	Orca	23 (30)	0
BIO-L1: Implantable Electronics	Port Alberni	48	0
Invited Session: INV-14: Advances in Speech Processing with Applications	Port Hardy	25	0
DSP-L12: Digital Signal Processing for Communications I	Port McNeill	20	2 [38]
11:15 - 12:45
ASP-L30: Analog-to-Digital Converters	Grand Ballroom A	43 (42)	1 [39]
ASP-L31: High-Frequency Amplifiers I	Grand Ballroom B	26 (30)	0
ASP-L32: RF Power Amplifiers	Grand Ballroom C	15	0
COMM-L10: Receivers Architecture and Design	Grand Ballroom D	43 (38)	1 [40]
VLSI-L19: Clocking	Junior Ballroom A/B	30 (35)	0
VLSI-L20: Memory	Junior Ballroom C	20	0
DSP-L13: Implementation of DSP Algorithms	Junior Ballroom D	32	0 [41]
NSA-L1: Neural Network Algorithms and Architectures	Finback	24 (20)	0
CAD-L10: New Areas in CAD I	Galiano	10	0
NLCS-L9: Switching Circuits and Systems: Bifurcation Analysis and Control	Granville	20	0 [42]
VSPC-L6: Scalable Video Coding	Orca	31 (20)	0
BIO-L2: Medical Sensors and Amplifiers	Port Alberni	54 (60)	0
Invited Session: INV-15: Behavioral Modeling and Analog and Mixed Signal Simulation	Port Hardy	21 (20)	0
DSP-L14: Digital Signal Processing for Communications II	Port McNeill	21 (25)	0
W E D N E S D A Y , M A Y 2 6 - S E S S I O N S - Afternoon
2:15 - 3:45
ASP-L33: Data Converters I	Grand Ballroom A	40	0
ASP-L34: Operational Amplifiers	Grand Ballroom B	28	0
ASP-L35: Signal Processing Building Blocks I	Grand Ballroom C	8 (12)	1 [43]
COMM-L11: RF Amplifiers for Communications	Grand Ballroom D	43 (40)	1 [44]
VLSI-L21: Current-Mode and Sensing	Junior Ballroom A/B	24	0
VLSI-L22: Flip-Flops	Junior Ballroom C	18	1 [45]
DSP-L15: Discrete-Time Transforms and Wavelets	Junior Ballroom D	15	0
NSA-L2: Neural Network Circuits and Systems I	Finback	28	0
CAD-L11: New Areas in CAD II	Galiano	10 (15)	2 [46]
NLCS-L10: Nonlinear Circuits and Arrays	Granville	13 (15)	0
VSPC-L7: Video Processing	Orca	20	2 [47]
BSP-L1: Blind Signal Processing I	Port Alberni	19	0
Invited Session: INV-16: Nonlinearity: Complexity and Noise	Port Hardy	20 (19)	0
DSP-L16: Audio and Speech Processing I	Port McNeill	20	0
4:00 - 5:30
ASP-L36: Computer Analysis and Synthesis	Grand Ballroom A	23 (25)	0
ASP-L37: Class AB amplifiers	Grand Ballroom B	33 (35)	0
ASP-L38: Signal Processing Building Blocks II	Grand Ballroom C	15 (25)	0
COMM-L13: RF Circuits and Systems	Grand Ballroom D	36 (30)	0
VLSI-L23: Test, Verification and Signal Processing	Junior Ballroom A/B	10	0
VLSI-L24: Frequency Synthesis, ESD	Junior Ballroom C	0	0 [48]
DSP-L17: Detection and Estimation	Junior Ballroom D	10	0
GTC-L1: Graph Algorithms and Applications I	Finback	22 (19)	1 [49]
COMM-L12: Clock/Data Recovery	Galiano	28 (25)	0
NLCS-L11: Applications of Nonlinear Circuits	Granville	15 (16)	1 [50]
VSPC-L8: Image Compression	Orca	15	1 [51]
NEGS-L1: Nanoelectronics and Gigascale Systems	Port Alberni	38 [52]	1 [53]
Invited Session: INV-17: Blind Signal Processing: BSS and ICA	Port Hardy	26	0
DSP-L18: Audio and Speech Processing II	Port McNeill	15	0
Monday, May 24 - POSTERS
(09:30 - 11:00)	Room	# Attendees	# Missing speakers
COMM-P1: Communication Architectures and Systems I	Poster Area 1		0
CAD-P1: CAD for Analog and Mixed Signal Circuits	Poster Area 2		1 [54]
DSP-P1: Digital Filters	Poster Area 3		1 [55]
DSP-P2: Digital Signal Processing I	Poster Area 4		0
ASP-P1: Analog Circuits in Systems I	Poster Area 5		0
ASP-P2: Analog Circuits in Systems II	Poster Area 6		0
VSPC-P1: 3-D and Image Processing	Poster Area 7		0
MMSA-P1: Data Hiding and Watermarking Techiques for Multimedia Systems	Poster Area 8		3 [56]
MMSA-P2: Intelligent Processing Techniques for Multimedia Systems and Applications	Poster Area 9		1 [57]
VLSI-P1: Low Power Design and Implementation I	Poster Area 10		2 [58]
11:15 - 12:45
NLCS-L2: PLLs Design, Implementation and Application Granville
COMM-P2: Communication Circuits Design I	Poster Area 1		0
CAD-P2: CAD for Digital Circuits	Poster Area 2		1 [59]
DSP-P3: Digital Filters and Filter Banks	Poster Area 3		0
DSP-P4: Digital Signal Processing II	Poster Area 4		0
NLCS-P1: Nonlinear Circuits Analysis and Design I	Poster Area 5		1 [60]
NLCS-P2: Nonlinear Circuits Analysis and Design II	Poster Area 6		0
VSPC-P2: General Image and Video Processing I	Poster Area 7		1 [61]
MMSA-P3: Communication and Coding Techniques for Multimedia Systems	Poster Area 8		0
MMSA-P4: VLSI/SOC Implementation for Multimidia Sytems II	Poster Area 9		0
VLSI-P2: Low Power Design and Implementation II	Poster Area 10		1 [62]
14:15 - 15:45
CAD-L3: Analog Modeling, Synthesis & Optimization I Galiano
COMM-P3: Computation Kernels and IP for Communication Systems I	Poster Area 1
CAD-P3: Testing, Verification, and Simulation	Poster Area 2
DSP-P5: Discrete-Time Transforms and Wavelets	Poster Area 3		0
DSP-P6: Digital Signal Processing III	Poster Area 4		0
CNN-P1: Circuit Design for Array Computers	Poster Area 5		0
ASP-P3: Controlled Amplifiers	Poster Area 6		1 [63]
ASP-P4: Current Amplifiers	Poster Area 7		1 [64]
ASP-P5: Analog Filtering I	Poster Area 8		0
ASP-P6: Analog Filtering II	Poster Area 9		1 [65]
VSPC-P3: General Image and Video Processing II	Poster Area 10		0
Tuesday, May 25 - POSTERS
09:30 - 11:00
VLSI-P3: Video IP Cores	Poster Area 1		0
CAD-P4: New Ideas in Physical Design	Poster Area 2		0
NSA-P1: Neural Systems and Applications II	Poster Area 3		1 [66]
SEN-P1: Network Sensors and MEMS	Poster Area 4		1 [67]
VSPC-P4: Image and Video Compression	Poster Area 5		0
DSP-P7: Digital Signal Processing for Communications	Poster Area 6		1 [68]
ASP-P7: Analog Circuits and Technology I	Poster Area 7		0
ASP-P8: Analog Circuits and Technology II	Poster Area 8		0
VLSI-P5: VLSI Architectures	Poster Area 9		1 [69]
VLSI-P4: Arithmetic Module Implementation	Poster Area 10		0
11:15 - 12:45
COMM-P4: Communication Circuits Design II	Poster Area 1		1 [70]
PSEC-P2: Control of Power Converters	Poster Area 2		2 [71]
PSEC-P3: Power Electronics Circuits	Poster Area 3		0
SEN-P2: Neuromorhic and Sensory Systems	Poster Area 4		0
BIO-P1: Biomedical Circuits and Systems I	Poster Area 5		0
DSP-P8: Digital Signal Processing IV	Poster Area 6		3 [72]
ASP-P9: Testing of Mixed Signal Circuits	Poster Area 7		0
ASP-P10: Mixed Signal and Sensor Interface Circuits	Poster Area 8		0
PSEC-P4: Analysis of Power Systems	Poster Area 9		3 [73]
PSEC-P1: Power Electronics and Systems	Poster Area 10	130	0
14:15 - 15:45
COMM-P5: Computation Kernels and IP for Communication Systems II	Poster Area 1	80	0
NSA-P2: Neural Network Circuits and Systems II	Poster Area 2
VLSI-P7: Arithmetic and Cryptography	Poster Area 3
SEN-P3: Image Sensors II	Poster Area 4
DSP-P9: Digital Signal Processing V	Poster Area 5
ASP-P11: RF Circuits I	Poster Area 6
ASP-P12: RF Circuits II	Poster Area 7
NLCS-P3: Nonlinear Circuits and Systems Analysis and Application I	Poster Area 8
NLCS-P4: Nonlinear Circuits and Systems Analysis and Application II	Poster Area 9
VLSI-P6: Arithmetic and DSP Implementation	Poster Area 10
Wednesday, May 26 - POSTERS
09:30 - 11:00
COMM-P6: Wireless Systems and High Speed Systems	Poster Area 1		0
ASP-P13: Analog Circuits I	Poster Area 2		1 [74]
ASP-P14: Analog Circuits II	Poster Area 3		2 [75]
ASP-P15: High-Frequency Amplifiers II	Poster Area 4		0
ASP-P16: Data Converters II	Poster Area 5		0
ASP-P17: Data Converters III	Poster Area 6		0
BSP-P1: Blind Signal Processing II	Poster Area 7		2 [76]
VLSI-P9: FPGA and PLA	Poster Area 8		0
VLSI-P10: Image Processing and Implementation	Poster Area 9		0
VLSI-P8: Circuit Design I	Poster Area 10		0
11:15 - 12:45
GTC-P1: Graph Algorithms and Applications II	Poster Area 1		0
ASP-P18: Analog Circuits III	Poster Area 2		0
ASP-P19: Analog Circuits IV	Poster Area 3		0
CNN-P2: Applications of Cellular Neural Networks and Array Computers	Poster Area 4		0
ASP-P20: Sigma-Delta Converters III	Poster Area 5		0
ASP-P21: Sigma-Delta Converters IV	Poster Area 6		0
BSP-P2: Blind Signal Processing III	Poster Area 7		0
NEGS-P1: Nanoelectronics and Nanoarchitecture	Poster Area 8		0
VLSI-P12: Array Architecture and SoC	Poster Area 9		0
VLSI-P11: Circuit Design II	Poster Area 10		0
14:15 - 15:45
Invited Session: INV-18: Information Assurance and Data Hiding II	Poster Area 1		0
Invited Session: INV-19: Silicon Implementations of CNN and Programmable Mixed-Signal Vision II	Poster Area 2		0
BIO-P2: Biomedical Circuits and Systems II	Poster Area 3		1 [77]
COMM-P7: Communication Architectures and Systems II	Poster Area 4		1 [78]
COMM-P8: Circuits and Networks for Communications	Poster Area 5	50	1 [79]
GTC-P2: Graph Algorithms and Applications III	Poster Area 6		0
NEGS-P2: Modeling and Simulation	Poster Area 7		0
NSA-P3: Neural Systems and Applications I	Poster Area 8		2 [80]
VSPC-P5: Video Coding	Poster Area 9		1 [81]
DSP-P10: Digital Signal Processing VI	Poster Area 10		1 [82]



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