CAD Tools for ICs

  • W. Maly, J. Gempel, D. Korzec, A.P. Piotrowski and M.S yrzycki, Statistical Simulation of VLSI IC Cell, Proc. of IEEE International Conference on Computer Aided Design, pp.254-255, 1983.
  • W. Maly, A.S wit and M. Syrzycki, Computer-Aided Design of Integrated Circuits in Process-Oriented Approach, (in Polish), Elektronika, No.10, pp.25-28, 1984.
  • D. Korzec, A. Wojtasik, M. Syrzycki, E. Piwowarska, W. Pleskacz, W. Kuzmicz, W. Maly, Device and Parasitic Oriented Circuit Extractor, SRC-CMU Research Report No.CMUCAD-87-31, Carnegie Mellon University, July 1987.
  • D. Korzec, A. Wojtasik, M. Syrzycki, E. Piwowarska, W. Pleskacz, W. Kuzmicz, W. Maly, Device and Parasitic Oriented Circuit Extractor, Proc. 1987 IEEE International Conference on Computer Design ICCD'87, Rye Brook, N.Y., pp. 430-433, October 1987.
  • W.  Kuzmicz, A. Pfitzner, A. Wojtasik, W. Pleskacz, E. Piwowarska, J. Gempel, M. Syrzycki , W. Maly, D. Korzec, K. Kozminski, LAPYSS: Layout Design and Process Yield Simulation System, Comp. Euro. 88, Brussels, April 11-14, 1988.
  • T.Liang, M.Syrzycki, Layout Generation Algorithm for CMOS Analog IC Cells, IEEE 1998 Canadian Conference on Electrical and Computer Engineering, CCECE'98, Waterloo, Ont., pp.653-656, May 24-28, 1998.
  • P. Khademsameni, M. Syrzycki, A Tool for Automated Analog CMOS Layout Module Generation and Placement, IEEE 2002 Canadian Conference on Electrical and Computer Engineering, CCECE'02, Winnipeg, Manitoba, May 12-15, 2002.


    For author's copy of the publication, send an e-mail to marek@cs.sfu.ca.