Concluding remarks
Main contribution is VHDL description of a 4x4 ATM switch
Switch has input buffers and prevents HOL blocking by utilizing virtual dynamic queues
Scheduler has a fair round robin algorithm (DPA)
Fabric consists of twelve 4x4 crossbar modules
VHDL implementation using ALTERA MAX+PLUS II tool
Switch fits on a single FLEX10KE device
Can be used as a module in ALTERA library