Dilshan Kumarathunga
MASc Student, Hardware Acceleration and Systems Engineer
Discovery II Building
8888 University Dr.
Simon Fraser University
Burnaby, BC V5A 1S6
Email: dilshan_kumarathunga [at] sfu.ca
I am a MASc student at the School of Engineering Science, Simon Fraser University. I am a member of the HiAccel lab, advised by Professor Zhenman Fang. My research interests include Computer Architecture, Hardware Accelerators, Reconfigurable Architectures, and Compiler Optimization.
I completed B.Sc. Eng (Hons.) in Electronic & Telecommunication Engineering at the University of Moratuwa, Sri Lanka. My final year undergraduate thesis project, which was done under the supervision of Dr. Ajith Pasqual and Dr. Ranga Rodrigo was accepted and published at ASAP 2019, titled "VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing". Here, we proposed an FPGA based application specific new architecture for machine vision related operations at the edge nodes.
After that, I had been working as a Senior Applications Engineer at Synopsys Inc., where I was engaged with the FPGA based emulation platform ZeBu, under different aspects like ZeBu front end, power estimation, simulation acceleration flow, and different ZeBu hardware. At Synopsys, I contributed to different projects involving many EDA tools as well as various HDL constructs and different customer scenarios.
What's New
- December 2025
- I successfully defended my thesis titled "AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs"
- November 2025
- "An Efficient and Scalable Hardware Architecture for Number Theoretic Transform on FPGA with Design Automation", a colloboration paper was accepted by HPCA 2026
- September 2025
- I received the Lang Wong Memorial Scholarship in Engineering
- June 2025
- I open-sourced our AutoNTT code to public. Welcome to use at AutoNTT GitHub
- April 2025
- "AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs" received the best paper nominee at FCCM 2025
- March 2025
- "AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs" was accepted by FCCM 2025
- January 2025
- I received the Supplemental Graduate Fellowship Award from Simon Fraser University
- September 2024
- I received the Graduate Fellowship Award from Simon Fraser University
- January 2024
- I received the Helmut & Hugo Eppich Family Graduate Scholarship for Intelligent Systems research
- October 2023
- Started research project: Number Theoretic Transform(NTT) Acceleration on FPGAs for Fully Homomorphic Encryption (FHE) applications
- September 2023
- I received the Graduate Fellowship Award from Simon Fraser University
- January 2023
- Started research project: Accelerating Sparse Triangular Solver(SpTRSV) on FPGAs
- September 2022
- Started graduate research at HiAccel Lab
- July 2019
- Presented and published the undergraduate thesis project paper at ASAP 2019
- February 2018
- Started working at Synopsys
- January 2018
- Completed B.Sc. Eng (Hons.) in Electronic & Telecommunication Engineering
- January 2014
- Started B.Sc. Eng (Hons.) in Electronic & Telecommunication Engineering at University of Moratuwa, Sri Lanka
Publications
Conference Papers
| C3 |
An Efficient and Scalable Hardware Architecture for Number Theoretic Transform on FPGA with Design Automation HPCA '26 |
| C2 |
AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs FCCM '25 Best Paper Nominee
Fully Homomorphic Encryption (FHE), which enables homomorphic computing on encrypted data, has emerged as a promising privacy-aware computing method. However, FHE is orders-of-magnitude slower than the same computation on plain data, making it far from practical use. One of the major computation bottlenecks in FHE is the Number Theoretic Transform (NTT). While prior studies have accelerated NTT using specific architectures and FHE parameters, there still lacks a design automation tool to systematically design and explore various NTT architectures to support a diverse range of FHE parameters, such as various polynomial sizes, modulo sizes, and reduction methods. In this paper, we present AutoNTT, an open-source automatic architecture design and exploration tool to generate highly scalable NTT accelerators on FPGAs. Unlike prior studies, AutoNTT can automatically generate several optimized NTT acceleration architectures in HLS (i.e., iterative, dataflow, and hybrid architectures) with multiple common reduction methods, and support a large range of polynomial sizes (2^10-2^17) and modulo sizes (logq:28−64). In our auto-generated NTT architectures, we have applied many optimizations, such as polynomial and twiddle factor buffer reduction, and simplifying interconnections between different butterfly unit groups. Compared to prior studies, AutoNTT can generate NTT accelerators with 2.48× better latency and 3.61× better throughput on average, while maintaining a similar FPGA resource utilization. AutoNTT will be released soon at https://github.com/SFU-HiAccel/AutoNTT.
@INPROCEEDINGS{AutoNTT-FCCM2025,
author={Kumarathunga, Dilshan and Hu, Qilin and Fang, Zhenman},
booktitle={2025 IEEE 33rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
title={AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs},
year={2025},
volume={},
number={},
pages={1-9},
keywords={Scalability;Computer architecture;Transforms;Throughput;Polynomials;Iterative algorithms;Space exploration;Resource management;Field programmable gate arrays;Optimization;number theoretic transform;fully homomorphic encryption;fpga acceleration;design automation;design space exploration},
doi={10.1109/FCCM62733.2025.00024}}
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| C1 |
VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing ASAP '19
The widespread use of high definition cameras for surveillance and related tasks has given rise to the concept of edge computing as transmitting and processing video streams in real time have become challenging. However, edge computing at low power and lower cost is difficult with general purpose processor hardware inside cameras. Finding a solution that meets the above requirements and demonstrates flexibility to handle diverse conditions is challenging. In this paper, we propose a coprocessor architecture which is specifically designed to perform machine vision related operations at the edge using very long instruction word (VLIW) architecture. It also supports multiple vision algorithms in the same hardware platform while supporting runtime reconfigurability, architectural flexibility, and extensibility. The system was practically realized on ZedBoard and verified for correct functionality and accuracy at 148.5 MHz. The system is capable of processing 1080p videos at 60 frames per second. Our system performs better than existing reconfigurable architectures and is on par with existing fixed architectures. The architecture can be implemented in the edge nodes of complex vision systems to increase the computational efficiency.
@INPROCEEDINGS{8825133, author={Kumarathunga, Dilshan and Gamage, Omega and Samarasinghe, Asitha and Saranga, Nipuna and Rodrigo, Ranga and Pasqual, Ajith}, booktitle={2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}, title={VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing}, year={2019}, volume={2160-052X}, number={}, pages={103-106}, doi={10.1109/ASAP.2019.00-22}}
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Contact
Please contact me via email: dilshan_kumarathunga [at] sfu.ca
Misc
In my free time, I like to read books, listen to music and watch movies.